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How to use create_interface method in tempest

Best Python code snippet using tempest_python

case_study_3.py

Source:case_study_3.py

...19oComp8  = oCca3.add_component(de.component.create('Comp8',  'Comp8'))20oComp9  = oCca4.add_component(de.component.create('Comp9',  'Comp9'))21oComp10 = oCca4.add_component(de.component.create('Comp10', 'Comp10'))22# Define interfaces on FPGA23oFpga1.create_interface('I1 to comp1')24oFpga1.create_interface('I2 to fpga2')25oFpga1.create_interface('I3 to comp2')26oFpga2.create_interface('I1')27oFpga2.create_interface('I1 to fpga3')28oFpga2.create_interface('I2 to comp2')29oFpga2.create_interface('I3 to fpga4')30oFpga2.create_interface('I4 to comp3')31oFpga3.create_interface('I1')32oFpga3.create_interface('I1 to fpga4')33oFpga3.create_interface('I2 to comp4')34oFpga3.create_interface('I3 to fpga5')35oFpga3.create_interface('I4 to comp5')36oFpga3.create_interface('I5 to comp6')37oFpga3.create_interface('I6 to comp7')38oFpga4.create_interface('I1')39oFpga4.create_interface('I2')40oFpga4.create_interface('I1 to comp8')41oFpga4.create_interface('I1 to comp9')42oFpga5.create_interface('I1')43oFpga5.create_interface('I1 to comp9')44oFpga5.create_interface('I2 to comp10')45# Define interfaces on components46oComp1.create_interface('I1')47oComp1.create_interface('I2')48oComp1.create_interface('I3')49oComp2.create_interface('I1')50oComp2.create_interface('I2')51oComp2.create_interface('I3')52oComp3.create_interface('I1')53oComp3.create_interface('I2')54oComp3.create_interface('I3')55oComp4.create_interface('I1')56oComp4.create_interface('I2')57oComp4.create_interface('I3')58oComp5.create_interface('I1')59oComp5.create_interface('I2')60oComp5.create_interface('I3')61oComp6.create_interface('I1')62oComp6.create_interface('I2')63oComp6.create_interface('I3')64oComp7.create_interface('I1')65oComp7.create_interface('I2')66oComp7.create_interface('I3')67oComp8.create_interface('I1')68oComp8.create_interface('I2')69oComp8.create_interface('I3')70oComp9.create_interface('I1')71oComp9.create_interface('I2')72oComp9.create_interface('I3')73oComp10.create_interface('I1')74oComp10.create_interface('I2')75oComp10.create_interface('I3')76# Add connections77# Add FPGA 1 connections78oCon1 = de.connection.create('con1', oCca1, 'FPGA1.I1 to comp1', 'Comp1.I1', False)79oCon2 = de.connection.create('con2', oCca1, 'FPGA1.I2 to fpga2', 'FPGA2.I1', False)80oCon3 = de.connection.create('con3', oCca1, 'FPGA1.I3 to comp2', 'Comp2.I1', False)81oCon4 = de.connection.create('con4', oSystem, 'cca1.FPGA2.I1 to fpga3', 'cca2.FPGA3.I1', False)82oCon5 = de.connection.create('con5', oCca1, 'FPGA2.I2 to comp2', 'Comp2.I2', False)83oCon6 = de.connection.create('con6', oSystem, 'cca1.FPGA2.I3 to fpga4', 'cca3.FPGA4.I1', False)84oCon7 = de.connection.create('con7', oCca1, 'FPGA2.I4 to comp3', 'Comp3.I1', False)85oCon8  = de.connection.create('con8',  oSystem, 'cca2.FPGA3.I1 to fpga4', 'cca3.FPGA4.I2', False)86oCon9  = de.connection.create('con9',  oCca2, 'FPGA3.I2 to comp4', 'Comp4.I1', False)87oCon10 = de.connection.create('con10', oSystem, 'cca2.FPGA3.I3 to fpga5', 'cca4.FPGA5.I1', False)88oCon11 = de.connection.create('con11', oCca2, 'FPGA3.I4 to comp5', 'Comp5.I1', False)89oCon12 = de.connection.create('con12', oCca2, 'FPGA3.I5 to comp6', 'Comp6.I1', False)...

case_study_2.py

Source:case_study_2.py

...16oComp8  = oCca.add_component(de.component.create('Comp8',  'Comp8'))17oComp9  = oCca.add_component(de.component.create('Comp9',  'Comp9'))18oComp10 = oCca.add_component(de.component.create('Comp10', 'Comp10'))19# Define interfaces on FPGA20oFpga1.create_interface('I1 to comp1')21oFpga1.create_interface('I2 to fpga2')22oFpga1.create_interface('I3 to comp2')23oFpga2.create_interface('I1')24oFpga2.create_interface('I1 to fpga3')25oFpga2.create_interface('I2 to comp2')26oFpga2.create_interface('I3 to fpga4')27oFpga2.create_interface('I4 to comp3')28oFpga3.create_interface('I1')29oFpga3.create_interface('I1 to fpga4')30oFpga3.create_interface('I2 to comp4')31oFpga3.create_interface('I3 to fpga5')32oFpga3.create_interface('I4 to comp5')33oFpga3.create_interface('I5 to comp6')34oFpga3.create_interface('I6 to comp7')35oFpga4.create_interface('I1')36oFpga4.create_interface('I2')37oFpga4.create_interface('I1 to comp8')38oFpga4.create_interface('I1 to comp9')39oFpga5.create_interface('I1')40oFpga5.create_interface('I1 to comp9')41oFpga5.create_interface('I2 to comp10')42# Define interfaces on components43oComp1.create_interface('I1')44oComp1.create_interface('I2')45oComp1.create_interface('I3')46oComp2.create_interface('I1')47oComp2.create_interface('I2')48oComp2.create_interface('I3')49oComp3.create_interface('I1')50oComp3.create_interface('I2')51oComp3.create_interface('I3')52oComp4.create_interface('I1')53oComp4.create_interface('I2')54oComp4.create_interface('I3')55oComp5.create_interface('I1')56oComp5.create_interface('I2')57oComp5.create_interface('I3')58oComp6.create_interface('I1')59oComp6.create_interface('I2')60oComp6.create_interface('I3')61oComp7.create_interface('I1')62oComp7.create_interface('I2')63oComp7.create_interface('I3')64oComp8.create_interface('I1')65oComp8.create_interface('I2')66oComp8.create_interface('I3')67oComp9.create_interface('I1')68oComp9.create_interface('I2')69oComp9.create_interface('I3')70oComp10.create_interface('I1')71oComp10.create_interface('I2')72oComp10.create_interface('I3')73# Add connections74# Add FPGA 1 connections75oCon1 = de.connection.create('con1', oCca, 'FPGA1.I1 to comp1', 'Comp1.I1', False)76oCon2 = de.connection.create('con2', oCca, 'FPGA1.I2 to fpga2', 'FPGA2.I1', False)77oCon3 = de.connection.create('con3', oCca, 'FPGA1.I3 to comp2', 'Comp2.I1', False)78oCon4 = de.connection.create('con4', oCca, 'FPGA2.I1 to fpga3', 'FPGA3.I1', False)79oCon5 = de.connection.create('con5', oCca, 'FPGA2.I2 to comp2', 'Comp2.I2', False)80oCon6 = de.connection.create('con6', oCca, 'FPGA2.I3 to fpga4', 'FPGA4.I1', False)81oCon7 = de.connection.create('con7', oCca, 'FPGA2.I4 to comp3', 'Comp3.I1', False)82oCon8  = de.connection.create('con8',  oCca, 'FPGA3.I1 to fpga4', 'FPGA4.I2', False)83oCon9  = de.connection.create('con9',  oCca, 'FPGA3.I2 to comp4', 'Comp4.I1', False)84oCon10 = de.connection.create('con10', oCca, 'FPGA3.I3 to fpga5', 'FPGA5.I1', False)85oCon11 = de.connection.create('con11', oCca, 'FPGA3.I4 to comp5', 'Comp5.I1', False)86oCon12 = de.connection.create('con12', oCca, 'FPGA3.I5 to comp6', 'Comp6.I1', False)...

topo_func_test.py

Source:topo_func_test.py

...62        azure1.config = f"{config_files[2]}"63        azure2 = lab.create_node("cloud2", "iosv", 100, 350)64        azure2.config = f"{config_files[3]}"65        # management links66        ext_i0 = ext.create_interface(slot=0)67        oob_i0 = oob.create_interface(slot=0)68        oob_i1 = oob.create_interface(slot=1)69        oob_i2 = oob.create_interface(slot=2)70        oob_i3 = oob.create_interface(slot=3)71        oob_i4 = oob.create_interface(slot=4)72        cloud1_i0 = cloud1.create_interface(slot=0)73        cloud2_i0 = cloud2.create_interface(slot=0)74        azure1_i0 = azure1.create_interface(slot=0)75        azure2_i0 = azure2.create_interface(slot=0)76        # inter router links77        cloud1_i1 = cloud1.create_interface(slot=1)78        cloud2_i1 = cloud2.create_interface(slot=1)79        cloud1_i2 = cloud1.create_interface(slot=2)80        cloud2_i2 = cloud2.create_interface(slot=2)81        azure1_i1 = azure1.create_interface(slot=1)82        azure2_i1 = azure2.create_interface(slot=1)83        azure1_i2 = azure1.create_interface(slot=2)84        azure2_i2 = azure2.create_interface(slot=2)85        # managment links to OOB switch from each router86        lab.create_link(ext_i0, oob_i0)87        lab.create_link(oob_i1, cloud1_i0)88        lab.create_link(oob_i2, cloud2_i0)89        lab.create_link(oob_i3, azure1_i0)90        lab.create_link(oob_i4, azure2_i0)91        # inter-router links92        lab.create_link(cloud1_i1, cloud2_i1)93        lab.create_link(cloud1_i2, azure1_i2)...

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