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How to use rs1 method in wpt

Best JavaScript code snippet using wpt

instructionParser.ts

Source:instructionParser.ts

1import { byteToHex } from '../../utils/helper';2import CPU_REGISTER_NAMES from '../../../bundled/yamls/register.yml';3export enum IMM_FUNC {4  ADDI = 0,5  SLLI = 1,6  SLTI = 2,7  SLTIU = 3,8  XORI = 4,9  SRLI = 5,10  SRAI = 5,11  ORI = 6,12  ANDI = 713}14export enum OP_FUNC3 {15  ADD = 0,16  SUB = 0,17  SLL = 1,18  SLT = 2,19  SLTU = 3,20  XOR = 4,21  SRL = 5,22  SRA = 5,23  OR = 6,24  AND = 725}26export enum BRANCH_FUNC {27  BEQ = 0,28  BNE = 1,29  BLT = 4,30  BGE = 5,31  BLTU = 6,32  BGEU = 733}34export enum LOAD_FUNC {35  LB = 0,36  LH = 1,37  LW = 2,38  LD = 3,39  LBU = 4,40  LHU = 5,41  LWU = 642}43export enum STORE_FUNC {44  SB = 0,45  SH = 1,46  SW = 2,47}48export enum SYSTEM_FUNC3 {49  ECALL = 0,50  EBREAK = 051}52/**53 * OPCODES 6:0 (1:0 are always 0x11) so they are ignored here54 */55export enum OPCODES {56  IMM = 0x04,57  LUI = 0x0D, // Direct58  AUIPC = 0x05, // Direct59  OP = 0x0C,60  JAL = 0x1B, // Direct61  JALR = 0x19, // Direct62  BRANCH = 0x18,63  LOAD = 0x00,64  STORE = 0x08,65  SYSTEM = 0x1C66}67export const OPCODE_FUNC3 = {68  [OPCODES.IMM]: IMM_FUNC,69  [OPCODES.OP]: OP_FUNC3,70  [OPCODES.BRANCH]: BRANCH_FUNC,71  [OPCODES.LOAD]: LOAD_FUNC,72  [OPCODES.STORE]: STORE_FUNC,73  [OPCODES.SYSTEM]: SYSTEM_FUNC374};75export enum INSTRUCTION_FORMATS {76  R = 'R', //       funct7 rs2 rs1 funct3          rd opcode77  I = 'I', //    imm[11:0]     rs1 funct3          rd opcode78  S = 'S', //    imm[11:5] rs2 rs1 funct3    imm[4:0] opcode79  B = 'B', // imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode80  U = 'U', //   imm[31:12]                         rd opcode81  J = 'J'  // imm[20|10:1|11|19:12]                rd opcode82}83export const OPCODE_INSTRUCTION_FORMAT = {84  [OPCODES.IMM]: INSTRUCTION_FORMATS.I,85  [OPCODES.OP]: INSTRUCTION_FORMATS.R,86  [OPCODES.BRANCH]: INSTRUCTION_FORMATS.B,87  [OPCODES.LOAD]: INSTRUCTION_FORMATS.I,88  [OPCODES.STORE]: INSTRUCTION_FORMATS.S,89  [OPCODES.SYSTEM]: INSTRUCTION_FORMATS.I,90  [OPCODES.JAL]: INSTRUCTION_FORMATS.J,91  [OPCODES.JALR]: INSTRUCTION_FORMATS.I,92  [OPCODES.AUIPC]: INSTRUCTION_FORMATS.U,93  [OPCODES.LUI]: INSTRUCTION_FORMATS.U94};95export const INSTRUCTIONS = {96  ADDI: 'ADDI',97  SLLI: 'SLLI',98  SLTI: 'SLTI',99  SLTIU: 'SLTIU',100  XORI: 'XORI',101  SRLI: 'SRLI',102  SRAI: 'SRAI',103  ORI: 'ORI',104  ANDI: 'ANDI',105  ADD: 'ADD',106  SUB: 'SUB',107  SLL: 'SLL',108  SLT: 'SLT',109  SLTU: 'SLTU',110  XOR: 'XOR',111  SRL: 'SRL',112  SRA: 'SRA',113  OR: 'OR',114  AND: 'AND',115  BEQ: 'BEQ',116  BNE: 'BNE',117  BLT: 'BLT',118  BGE: 'BGE',119  BLTU: 'BLTU',120  BGEU: 'BGEU',121  LB: 'LB',122  LH: 'LH',123  LW: 'LW',124  LBU: 'LBU',125  LHU: 'LHU',126  SB: 'SB',127  SH: 'SH',128  SW: 'SW',129  ECALL: 'ECALL',130  EBREAK: 'EBREAK',131  JAL: 'JAL',132  JALR: 'JALR',133  AUIPC: 'AUIPC',134  LUI: 'LUI'135};136export const INSTRUCTIONS_DESCRIPTIONS = {137  [INSTRUCTIONS.ADDI]: {138    name: 'addi',139    desc: 'Add immediate',140    text: 'Takes the value at register location RS1, adds the immediate value (IMM) and stores it back to the register at location RD.',141    formula: 'rd = rs1 + imm',142    rs1: true,143    rs2: false,144    imm: true,145    rd: true,146  },147  [INSTRUCTIONS.SLLI]: {148    name: 'slli',149    desc: 'Shift Left Logical Imm',150    text: 'Takes the value at register location RS1, shifts it to the left by the amount of immediate value (IMM) and stores it back to the register at location RD.',151    formula: 'rd = rs1 << imm[0:4]',152    rs1: true,153    rs2: false,154    imm: true,155    rd: true,156  },157  [INSTRUCTIONS.SLTI]: {158    name: 'slti',159    desc: 'Set Less Than Imm',160    text: 'Takes the value at register location RS1 and compares it to the immediate value (IMM). If the value of RS1 is smaller than IMM, store 1 back to the register at location RD, else store a 0.',161    formula: 'rd = (rs1 < imm)?1:0',162    rs1: true,163    rs2: false,164    imm: true,165    rd: true,166  },167  [INSTRUCTIONS.SLTIU]: {168    name: 'sltiu',169    desc: 'Set Less Than Imm (U)',170    text: 'Takes the value at register location RS1 and compares it to the immediate value (IMM). If the value of RS1 is smaller than IMM, store 1 back to the register at location RD, else store a 0.',171    formula: 'rd = (rs1 < imm)?1:0',172    rs1: true,173    rs2: false,174    imm: true,175    rd: true,176  },177  [INSTRUCTIONS.XORI]: {178    name: 'xori',179    desc: 'Exclusive OR Immediate',180    text: 'Takes the value at register location RS1, performs a "bitwise exclusive or" (XOR) operation with the immediate value and stores the result back to the register at location RD.',181    formula: 'rd = rs1 Ë imm',182    rs1: true,183    rs2: false,184    imm: true,185    rd: true,186  },187  [INSTRUCTIONS.SRLI]: {188    name: 'srli',189    desc: 'Shift Right Logical Imm',190    formula: 'rd = rs1 >> imm[0:4]',191    text: 'Takes the value at register location RS1, shifts it to the right by the amount of immediate value (IMM) and stores it back to the register at location RD.',192    rs1: true,193    rs2: false,194    imm: true,195    rd: true,196  },197  [INSTRUCTIONS.SRAI]: {198    name: 'srai',199    desc: 'Shift Right Arith. Imm',200    text: 'Takes the value at register location RS1, shifts it to the right by the amount of immediate value (IMM) and stores it back to the register at location RD.',201    formula: 'rd = rs1 >> imm[0:4]',202    rs1: true,203    rs2: false,204    imm: true,205    rd: true,206  },207  [INSTRUCTIONS.ORI]:  {208    name: 'ori',209    desc: 'OR Immediate',210    text: 'Takes the value at register location RS1, performs a "bitwise or" (OR) operation with the immediate value and stores the result back to the register at location RD.',211    formula: 'rd = rs1 | imm',212    rs1: true,213    rs2: false,214    imm: true,215    rd: true,216  },217  [INSTRUCTIONS.ANDI]:  {218    name: 'andi',219    desc: 'AND Immediate',220    text: 'Takes the value at register location RS1, performs a "bitwise and" (AND) operation with the immediate value and stores the result back to the register at location RD.',221    formula: 'rd = rs1 & imm',222    rs1: true,223    rs2: false,224    imm: true,225    rd: true,226  },227  [INSTRUCTIONS.ADD]: {228    name: 'add',229    desc: 'ADD',230    formula: 'rd = rs1 + rs2',231    rs1: true,232    rs2: true,233    imm: false,234    rd: true,235  },236  [INSTRUCTIONS.SUB]: {237    name: 'sub',238    desc: 'SUB',239    formula: 'rd = rs1 - rs2',240    rs1: true,241    rs2: true,242    imm: false,243    rd: true,244  },245  [INSTRUCTIONS.SLL]: {246    name: 'sll',247    desc: 'Shift Left Locical',248    formula: 'rd = rs1 << rs2',249    rs1: true,250    rs2: true,251    imm: false,252    rd: true,253  },254  [INSTRUCTIONS.SLT]: {255    name: 'slt',256    desc: 'Set Less Than',257    formula: 'rd = (rs1 < rs2)?1:0',258    rs1: true,259    rs2: true,260    imm: false,261    rd: true,262  },263  [INSTRUCTIONS.SLTU]: {264    name: 'sltu',265    desc: 'Set Less Than (U)',266    formula: 'rd = (rs1 < rs2)?1:0',267    rs1: true,268    rs2: true,269    imm: false,270    rd: true,271  },272  [INSTRUCTIONS.XOR]: {273    name: 'xor',274    desc: 'XOR',275    formula: 'rd = rs1 Ë rs2',276    rs1: true,277    rs2: true,278    imm: false,279    rd: true,280  },281  [INSTRUCTIONS.SRL]: {282    name: 'srl',283    desc: 'Shift Right Logical',284    formula: 'rd = rs1 >> rs2',285    rs1: true,286    rs2: true,287    imm: false,288    rd: true,289  },290  [INSTRUCTIONS.SRA]: {291    name: 'sra',292    desc: 'Shift Right Arith.',293    formula: 'rd = rs1 >> rs2',294    rs1: true,295    rs2: true,296    imm: false,297    rd: true,298  },299  [INSTRUCTIONS.OR]: {300    name: 'or',301    desc: 'OR',302    formula: 'rd = rs1 | rs2',303    rs1: true,304    rs2: true,305    imm: false,306    rd: true,307  },308  [INSTRUCTIONS.AND]: {309    name: 'and',310    desc: 'AND',311    formula: 'rd = rs1 & rs2',312    rs1: true,313    rs2: true,314    imm: false,315    rd: true,316  },317  [INSTRUCTIONS.BEQ]: {318    name: 'beq',319    desc: 'Branch Equal',320    formula: 'if(rs1 == rs2) PC += imm',321    rs1: true,322    rs2: true,323    imm: true,324    rd: false,325  },326  [INSTRUCTIONS.BNE]: {327    name: 'bne',328    desc: 'Branch Not Equal',329    formula: 'if(rs1 != rs2) PC += imm',330    rs1: true,331    rs2: true,332    imm: true,333    rd: false,334  },335  [INSTRUCTIONS.BLT]: {336    name: 'blt',337    desc: 'Branch Lower Than',338    formula: 'if(rs1 < rs2) PC += imm',339    rs1: true,340    rs2: true,341    imm: true,342    rd: false,343  },344  [INSTRUCTIONS.BGE]: {345    name: 'bge',346    desc: 'Branch Greater Equal',347    formula: 'if(rs1 >= rs2) PC += imm',348    rs1: true,349    rs2: true,350    imm: true,351    rd: false,352  },353  [INSTRUCTIONS.BLTU]: {354    name: 'bltu',355    desc: 'Branch Lower Than (U)',356    formula: 'if(rs1 < rs2) PC += imm',357    rs1: true,358    rs2: true,359    imm: true,360    rd: false,361  },362  [INSTRUCTIONS.BGEU]: {363    name: 'bgeu',364    desc: 'Branch Greater Equal (U)',365    formula: 'if(rs1 >= rs2) PC += imm',366    rs1: true,367    rs2: true,368    imm: true,369    rd: false,370  },371  [INSTRUCTIONS.LB]: {372    name: 'lb',373    desc: 'Load Byte',374    formula: 'rd = M[rs1+imm][0:7]',375    rs1: true,376    rs2: false,377    imm: true,378    rd: true,379  },380  [INSTRUCTIONS.LH]: {381    name: 'lh',382    desc: 'Load Half',383    formula: 'rd = M[rs1+imm][0:15]',384    rs1: true,385    rs2: false,386    imm: true,387    rd: true,388  },389  [INSTRUCTIONS.LW]: {390    name: 'lw',391    desc: 'Load Word',392    formula: 'rd = M[rs1+imm][0:31]',393    rs1: true,394    rs2: false,395    imm: true,396    rd: true,397  },398  [INSTRUCTIONS.LBU]: {399    name: 'ld',400    desc: 'Load Word',401    formula: 'rd = M[rs1+imm][0:31]',402    rs1: true,403    rs2: false,404    imm: true,405    rd: true,406  },407  [INSTRUCTIONS.LHU]: {408    name: 'lhu',409    desc: 'Load Half (U)',410    formula: 'rd = M[rs1+imm][0:15]',411    rs1: true,412    rs2: false,413    imm: true,414    rd: true,415  },416  [INSTRUCTIONS.SB]: {417    name: 'sb',418    desc: 'Store Byte',419    formula: 'M[rs1+imm][0:7] = rs2[0:7]',420    text: 'Store a 8 bit value from register source 2 to the memory at location of register source 1 plus immediate.',421    rs1: true,422    rs2: true,423    imm: true,424    rd: false,425  },426  [INSTRUCTIONS.SH]: {427    name: 'sh',428    desc: 'Store Half',429    formula: 'M[rs1+imm][0:15] = rs2[0:15]',430    text: 'Store a 16 bit value from register source 2 to the memory at location of register source 1 plus immediate.',431    rs1: true,432    rs2: true,433    imm: true,434    rd: false,435  },436  [INSTRUCTIONS.SW]: {437    name: 'sw',438    desc: 'Store Word',439    formula: 'M[rs1+imm][0:31] = rs2[0:31]',440    text: 'Store a 32 bit value from register source 2 to the memory at location of register source 1 plus immediate.',441    rs1: true,442    rs2: true,443    imm: true,444    rd: false,445  },446  [INSTRUCTIONS.ECALL]: {447    name: 'ecall',448    desc: 'Environment Call',449    formula: 'Transfer control',450    rs1: false,451    rs2: false,452    imm: false,453    rd: false,454  },455  [INSTRUCTIONS.EBREAK]: {456    name: 'ebreak',457    desc: 'Environment Break',458    formula: 'Transfer control',459    rs1: false,460    rs2: false,461    imm: false,462    rd: false,463  },464  [INSTRUCTIONS.JAL]: {465    name: 'jal',466    desc: 'Jump And Link',467    formula: 'rd = PC + 4; PC += imm',468    text: 'Save the next instruction address to the destination register and jump to a new address given by the immediate value plus the current program counter. The assembly of the instruction will show the address to jump to in hexadecimal.',469    rs1: false,470    rs2: false,471    imm: true,472    rd: true,473  },474  [INSTRUCTIONS.JALR]: {475    name: 'jalr',476    desc: 'Jump And Link Ref',477    formula: 'rd = PC + 4; PC = rs1 + imm',478    text: 'Save the next instruction address to the destination register and jump to a new absolute address set by register source 1 plus the immediate value.',479    rs1: true,480    rs2: false,481    imm: true,482    rd: true,483  },484  [INSTRUCTIONS.AUIPC]: {485    name: 'auipc',486    desc: 'Add Upper Imm to PC',487    formula: 'rd = PC + (imm << 12)',488    text: 'Shift the immediate value twelve to the right, add the program counter and save it to the destination register.',489    rs1: false,490    rs2: false,491    imm: true,492    rd: true,493  },494  [INSTRUCTIONS.LUI]: {495    name: 'lui',496    desc: 'Load Upper Imm',497    formula: 'rd = imm << 12',498    text: 'Shift the immediate value twelve to the right and save it to the destination register. Used to load big values.',499    rs1: false,500    rs2: false,501    imm: true,502    rd: true,503  },504};505export interface Instruction {506  /** Unparsed number value of instruction **/507  unparsedInstruction: number;508  /** Instruction type format **/509  instructionTypeFormat: INSTRUCTION_FORMATS;510  /** Opcode of the instruction, groups instruction **/511  opcode: OPCODES;512  /** Opcode of the instruction, groups instruction **/513  opcodeName: string;514  /** Func3 number value **/515  func3: OP_FUNC3 | BRANCH_FUNC | STORE_FUNC | LOAD_FUNC | IMM_FUNC;516  /** Func7 number value **/517  func7: any;518  /** Register destination **/519  rd: number;520  /** Register source 1 **/521  rs1: number;522  /** Register source 2 **/523  rs2: number;524  /** Immediate Value */525  imm: number;526  /** Immediate value if I type instruction format **/527  immI: number;528  /** Immediate value if S type instruction format **/529  immS: number;530  /** Immediate value if B type instruction format **/531  immB: number;532  /** Immediate value if U type instruction format **/533  immU: number;534  /** Immediate value if J type instruction format **/535  immJ: number;536  /** Name of the instruction e.g. ADD, ADDI, LUI ... **/537  instructionName: string;538  /** Description of the instruction **/539  description: object;540  /** Where in memory this instruction is saved, not filled by this parser but by an elf loader **/541  pc?: number;542  /** Assembly of the instruction as shown by objdump **/543  assembly?: string;544}545export function convertToSigned(bitnumber, bitlenght): number {546  const mask = 2 ** (bitlenght - 1);547  return -(bitnumber & mask) + (bitnumber & ~mask);548}549const NAME_LOOKUP_TABLE = {550  [OPCODES.IMM]: {551    [IMM_FUNC.ADDI]: INSTRUCTIONS.ADDI,552    [IMM_FUNC.SLLI]: INSTRUCTIONS.SLLI,553    [IMM_FUNC.SLTI]: INSTRUCTIONS.SLTI,554    [IMM_FUNC.SLTIU]: INSTRUCTIONS.SLTIU,555    [IMM_FUNC.XORI]: INSTRUCTIONS.XORI,556    [IMM_FUNC.SRLI]: {557      0x00: INSTRUCTIONS.SRAI,558      0x20: INSTRUCTIONS.SRLI559    },560    [IMM_FUNC.ORI]: INSTRUCTIONS.ORI,561    [IMM_FUNC.ANDI]: INSTRUCTIONS.ANDI562  },563  [OPCODES.OP]: {564    [OP_FUNC3.ADD]: {565      0x00: INSTRUCTIONS.ADD,566      0x20: INSTRUCTIONS.SUB567    },568    [OP_FUNC3.SLL]: INSTRUCTIONS.SLL,569    [OP_FUNC3.SLT]: INSTRUCTIONS.SLT,570    [OP_FUNC3.SLTU]: INSTRUCTIONS.SLTU,571    [OP_FUNC3.XOR]: INSTRUCTIONS.XOR,572    [OP_FUNC3.SRL]: {573      0x00: INSTRUCTIONS.SRL,574      0x20: INSTRUCTIONS.SRA575    },576    [OP_FUNC3.OR]: INSTRUCTIONS.OR,577    [OP_FUNC3.AND]: INSTRUCTIONS.AND578  },579  [OPCODES.BRANCH]: {580    [BRANCH_FUNC.BEQ]: INSTRUCTIONS.BEQ,581    [BRANCH_FUNC.BNE]: INSTRUCTIONS.BNE,582    [BRANCH_FUNC.BLT]: INSTRUCTIONS.BLT,583    [BRANCH_FUNC.BGE]: INSTRUCTIONS.BGE,584    [BRANCH_FUNC.BLTU]: INSTRUCTIONS.BLTU,585    [BRANCH_FUNC.BGEU]: INSTRUCTIONS.BGEU586  },587  [OPCODES.LOAD]: {588    [LOAD_FUNC.LB]: INSTRUCTIONS.LB,589    [LOAD_FUNC.LH]: INSTRUCTIONS.LH,590    [LOAD_FUNC.LW]: INSTRUCTIONS.LW,591    [LOAD_FUNC.LBU]: INSTRUCTIONS.LBU,592    [LOAD_FUNC.LHU]: INSTRUCTIONS.LHU,593  },594  [OPCODES.STORE]: {595    [STORE_FUNC.SB]: INSTRUCTIONS.SB,596    [STORE_FUNC.SH]: INSTRUCTIONS.SH,597    [STORE_FUNC.SW]: INSTRUCTIONS.SW598  },599  [OPCODES.SYSTEM]: {600    [SYSTEM_FUNC3.ECALL]: {601      0x00: INSTRUCTIONS.ECALL,602      0x01: INSTRUCTIONS.EBREAK603    }604  },605  [OPCODES.JAL]: INSTRUCTIONS.JAL,606  [OPCODES.JALR]: INSTRUCTIONS.JALR,607  [OPCODES.AUIPC]: INSTRUCTIONS.AUIPC,608  [OPCODES.LUI]: INSTRUCTIONS.LUI609};610export function getNameFromInstruction(opcode, func3, func7, imm): string {611  try {612    let op = null;613    if (opcode == OPCODES.SYSTEM) {614      return NAME_LOOKUP_TABLE[opcode][func3][imm];615    } else {616      op = NAME_LOOKUP_TABLE[opcode];617      if (typeof op !== 'string') op = op[func3];618      if (typeof op !== 'string') op = op[func7];619      return op;620    }621  } catch (e) {622    console.log("Could not find instruction name for", opcode, e);623  }624  return 'unimplemented';625}626export function isIMM(name: string): boolean {627  return name === INSTRUCTIONS.ADDI ||628    name === INSTRUCTIONS.XORI ||629    name === INSTRUCTIONS.ORI ||630    name === INSTRUCTIONS.ANDI ||631    name === INSTRUCTIONS.SLLI ||632    name === INSTRUCTIONS.SRLI ||633    name === INSTRUCTIONS.SRAI ||634    name === INSTRUCTIONS.SLTI ||635    name === INSTRUCTIONS.SLTIU;636}637export function isOP(name: string): boolean {638  return name === INSTRUCTIONS.ADD ||639    name === INSTRUCTIONS.SUB ||640    name === INSTRUCTIONS.XOR ||641    name === INSTRUCTIONS.OR ||642    name === INSTRUCTIONS.AND ||643    name === INSTRUCTIONS.SLL ||644    name === INSTRUCTIONS.SRL ||645    name === INSTRUCTIONS.SRA ||646    name === INSTRUCTIONS.SLT ||647    name === INSTRUCTIONS.SLTU;648}649export function isLOAD(name: string): boolean {650  return name === INSTRUCTIONS.LB ||651    name === INSTRUCTIONS.LH ||652    name === INSTRUCTIONS.LW ||653    name === INSTRUCTIONS.LBU ||654    name === INSTRUCTIONS.LHU;655}656export function isSTORE(name: string): boolean {657  return name === INSTRUCTIONS.SB ||658    name === INSTRUCTIONS.SH ||659    name === INSTRUCTIONS.SW;660}661export function isBRANCH(name: string): boolean {662  return name === INSTRUCTIONS.BEQ ||663    name === INSTRUCTIONS.BNE ||664    name === INSTRUCTIONS.BLT ||665    name === INSTRUCTIONS.BGE ||666    name === INSTRUCTIONS.BLTU ||667    name === INSTRUCTIONS.BGEU;668}669export function isJAL(name: string): boolean {670  return name === INSTRUCTIONS.JAL671}672export function isJALR(name: string): boolean {673  return name === INSTRUCTIONS.JALR674}675export function isLUI(name: string): boolean {676  return name === INSTRUCTIONS.LUI677}678export function isAUIPC(name: string): boolean {679  return name === INSTRUCTIONS.AUIPC680}681export function isSystem(name: string): boolean {682  return name === INSTRUCTIONS.ECALL || name === INSTRUCTIONS.EBREAK;683}684export function getNameOfGroup(opcode): 'imm' | 'op' | 'lui' | 'auipc' | 'jal' | 'jalr' | 'load' | 'store' | 'branch' | 'system' {685  if (opcode === OPCODES.IMM) return 'imm';686  if (opcode === OPCODES.OP) return 'op';687  if (opcode === OPCODES.LUI) return 'lui';688  if (opcode === OPCODES.AUIPC) return 'auipc';689  if (opcode === OPCODES.JAL) return 'jal';690  if (opcode === OPCODES.JALR) return 'jalr';691  if (opcode === OPCODES.LOAD) return 'load';692  if (opcode === OPCODES.STORE) return 'store';693  if (opcode === OPCODES.BRANCH) return 'branch';694  if (opcode === OPCODES.SYSTEM) return 'system';695}696/**697 * Parses a instruction e.g. 0x058000ef. BigEndian encoding.698 * @param instruction The instruction encoded in big endian as a number699 */700export function parseInstruction(instruction, addr = 0): Instruction {701  const always11 = (instruction) & 0b11; // The first two bits are always 11702  const opcode = (instruction >> 2) & 0b11111;703  const type = OPCODE_INSTRUCTION_FORMAT[opcode];704  let rd = null;705  if (type === INSTRUCTION_FORMATS.R706    || type === INSTRUCTION_FORMATS.I707    || type === INSTRUCTION_FORMATS.U708    || type === INSTRUCTION_FORMATS.J) {709    rd = (instruction >> 7) & 0b11111;710  }711  let func3: OP_FUNC3 | BRANCH_FUNC | STORE_FUNC | LOAD_FUNC | IMM_FUNC = null;712  let rs1 = null;713  if (type === INSTRUCTION_FORMATS.R714    || type === INSTRUCTION_FORMATS.I715    || type === INSTRUCTION_FORMATS.S716    || type === INSTRUCTION_FORMATS.B) {717    func3 = (instruction >> 12) & 0b111;718    rs1 = (instruction >> 15) & 0b11111;719  }720  let func7: number = null;721  if (type === INSTRUCTION_FORMATS.R) {722    func7 = (instruction >> 25) & 0b1111111;723  }724  let rs2: number = null;725  if (type === INSTRUCTION_FORMATS.R726    || type === INSTRUCTION_FORMATS.S727    || type === INSTRUCTION_FORMATS.B) {728    rs2 = (instruction >> 20) & 0b11111;729  }730  // All possible immediate allValues731  let immI: number = null;732  immI = (instruction >> 20) & 0b111111111111;733  immI = convertToSigned(immI, 12);734  let immS: number = null;735  immS = ((instruction >> 7) & 0b11111) + (((instruction >> 25) & 0b1111111) << 5);736  immS = convertToSigned(immS, 12);737  let immB: number = null;738  immB = (((instruction >> 31) & 0b1) << 12)739    + (((instruction >> 25) & 0b111111) << 5)740    + (((instruction >> 7) & 0b1) << 11)741    + (((instruction >> 8) & 0b1111) << 1);742  immB = convertToSigned(immB, 13);743  let immU: number = null;744  immU = (instruction >> 12) & 0b11111111111111111111;745  immU = convertToSigned(immU, 32);746  let immJ: number = null;747  immJ = (((instruction >> 31) & 0b1) << 20)748    + (((instruction >> 21) & 0b1111111111) << 1)749    + (((instruction >> 20) & 0b1) << 11)750    + (((instruction >> 12) & 0b11111111) << 12);751  immJ = convertToSigned(immJ, 21);752  // The immediate value selected corresponding to the instruction753  let imm: number = null;754  switch (type) {755    case INSTRUCTION_FORMATS.I:756      imm = immI;757      break;758    case INSTRUCTION_FORMATS.S:759      imm = immS;760      break;761    case INSTRUCTION_FORMATS.B:762      imm = immB;763      break;764    case INSTRUCTION_FORMATS.U:765      imm = immU;766      break;767    case INSTRUCTION_FORMATS.J:768      imm = immJ;769      break;770    default:771      imm = null;772  }773  const name = getNameFromInstruction(opcode, func3, func7, imm);774  const description = INSTRUCTIONS_DESCRIPTIONS[name];775  const rdString = description.rd ? CPU_REGISTER_NAMES[rd][0] : '';776  const rs1String = description.rs1 ? CPU_REGISTER_NAMES[rs1][0] : '';777  const rs2String = description.rs2 ? CPU_REGISTER_NAMES[rs2][0] : '';778  let assembly;779  switch (opcode) {780    case OPCODES.STORE:781      assembly = `${name.toLowerCase()} ${rs2String},${imm}(${rs1String})`782      break;783    case OPCODES.JALR:784    case OPCODES.LOAD:785      assembly = `${name.toLowerCase()} ${rdString},${imm}(${rs1String})`786      break;787    case OPCODES.JAL:788      assembly = `${name.toLowerCase()} ${rdString},${byteToHex(imm + addr, 0).toLowerCase()}`789      break;790    case OPCODES.BRANCH:791      assembly = `${name.toLowerCase()} ${rs1String},${rs2String},${byteToHex(imm + addr, 0).toLowerCase()}`792      break;793    case OPCODES.SYSTEM:794      assembly = `${name.toLowerCase()}`795      break;796    case OPCODES.LUI:797    case OPCODES.AUIPC:798      assembly = `${name.toLowerCase()} ${rdString},0x${byteToHex(imm, 0).toLowerCase()}`799      break;800    default:801      assembly = `${name.toLowerCase()}${description.rd ? (' ' + rdString) : ''}${description.rs1 ? (',' + rs1String) : ''}${description.rs2 ? (',' + rs2String) : ''}${description.imm ? (',' + imm) : ''}`802  }803  const parsedInstruction: Instruction = {804    unparsedInstruction: instruction,805    instructionTypeFormat: type,806    opcode: opcode,807    opcodeName: getNameOfGroup(opcode),808    func3: func3,809    func7: func7,810    imm: imm,811    immI: immI,812    immS: immS,813    immB: immB,814    immU: immU,815    immJ: immJ,816    rd: rd,817    rs1: rs1,818    rs2: rs2,819    instructionName: name,820    description: description,821    assembly: assembly,822  };823  return parsedInstruction;...

Instruction.ts

Source:Instruction.ts

1// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 002// {       funct7     } {     rs2    } {     rs1    } {  f3  } {      rd    } {      opcode      }   R Type3// {             imm[11:0]           } {     rs1    } {  f3  } {      rd    } {      opcode      }   I Type4// {     imm[11:5]    } {     rs2    } {     rs1    } {  f3  } {  imm[4:0]  } {      opcode      }   S Type5import { getBits, maskBits, unsignedSlice } from "../../utils/bits";6import { SymbolTable } from "./ByteCodeGenerator";7// prettier-ignore8export const operations = {9  //       fmt  opcode     f3   f710  add:   [ "R", 0b0110011, 0x0, 0x00 ], // __ rd, rs1, rs2 11  sub:   [ "R", 0b0110011, 0x0, 0x20 ], // __ rd, rs1, rs212  xor:   [ "R", 0b0110011, 0x4, 0x00 ], // __ rd, rs1, rs213  or:    [ "R", 0b0110011, 0x6, 0x00 ], // __ rd, rs1, rs214  and:   [ "R", 0b0110011, 0x7, 0x00 ], // __ rd, rs1, rs215  sll:   [ "R", 0b0110011, 0x1, 0x00 ], // __ rd, rs1, rs216  srl:   [ "R", 0b0110011, 0x5, 0x00 ], // __ rd, rs1, rs217  sra:   [ "R", 0b0110011, 0x5, 0x20 ], // __ rd, rs1, rs218  slt:   [ "R", 0b0110011, 0x2, 0x00 ], // __ rd, rs1, rs219  sltu:  [ "R", 0b0110011, 0x3, 0x00 ], // __ rd, rs1, rs220  addi:  [ "I", 0b0010011, 0x0,      ], // __ rd, rs1, imm21  xori:  [ "I", 0b0010011, 0x4,      ], // __ rd, rs1, imm22  ori:   [ "I", 0b0010011, 0x6,      ], // __ rd, rs1, imm23  andi:  [ "I", 0b0010011, 0x7,      ], // __ rd, rs1, imm24  slli:  [ "I", 0b0010011, 0x1,      ], // __ rd, rs1, imm25  srli:  [ "I", 0b0010011, 0x5,      ], // __ rd, rs1, imm26  srai:  [ "I", 0b0010011, 0x5,      ], // __ rd, rs1, imm27  slti:  [ "I", 0b0010011, 0x2,      ], // __ rd, rs1, imm28  sltiu: [ "I", 0b0010011, 0x3,      ], // __ rd, rs1, imm29  lb:    [ "I", 0b0000011, 0x0,      ], // l__ rd, rs1, imm30  lh:    [ "I", 0b0000011, 0x1,      ], // l__ rd, rs1, imm31  lw:    [ "I", 0b0000011, 0x2,      ], // l__ rd, rs1, imm32  lbu:   [ "I", 0b0000011, 0x4,      ], // l__ rd, rs1, imm33  lhu:   [ "I", 0b0000011, 0x5,      ], // l__ rd, rs1, imm34  sb:    [ "S", 0b0100011, 0x0,      ], // s_  rs1, rs2, imm35  sh:    [ "S", 0b0100011, 0x1,      ], // s_  rs1, rs2, imm36  sw:    [ "S", 0b0100011, 0x2,      ], // s_  rs1, rs2, imm37  beq:   [ "B", 0b1100011, 0x0,      ], // b__ rs1, rs2, imm 38  bne:   [ "B", 0b1100011, 0x1,      ], // b__ rs1, rs2, imm39  blt:   [ "B", 0b1100011, 0x4,      ], // b__ rs1, rs2, imm40  bge:   [ "B", 0b1100011, 0x5,      ], // b__ rs1, rs2, imm41  bltu:  [ "B", 0b1100011, 0x6,      ], // b__ rs1, rs2, imm42  bgeu:  [ "B", 0b1100011, 0x7,      ], // b__ rs1, rs2, imm43  jal:   [ "J", 0b1101111,    ,      ], // jal rd, imm44  jalr:  [ "I", 0b1100111, 0x0,      ], // jalr rd, rs1, imm45  lui:   [ "U", 0b0110111,    ,      ],46  auipc: [ "U", 0b0010111,    ,      ],47  ecall: [ "I", 0b1110011, 0x0,      ]48}49const instructionFields = {50  all: maskBits(0,31),51  opcode: maskBits(0,6),52  funct3: maskBits(12,14),53  funct5: maskBits(27,13),54  funct7: maskBits(25,31),55  rd: maskBits(7,11),56  rs1: maskBits(15, 19),57  rs2: maskBits(20, 24),58  rs3: maskBits(27, 31),59  imm_11_0: maskBits(20,31),60  imm_4_0: maskBits(7,11),61  imm_11_5: maskBits(25,31),62  imm_11b: maskBits(7),63  imm_4_1: maskBits(8, 11),64  imm_10_5: maskBits(25, 30),65  imm_12: maskBits(31),66  imm_31_12: maskBits(12, 31),67  imm_19_12: maskBits(12, 19),68  imm_11j: maskBits(20),69  imm_10_1: maskBits(21, 30),70  imm_20: maskBits(31)71}72type InstructionType = "I" | "R" | "S" | "B" | "J" | "U";73interface InstructionParameters {74  rs1?: number;75  rs2?: number;76  rd?: number;77  imm?: number;78  offset?: number | string;79  symbol?: string;80  macro?: "hi" | "lo"81}82export class Instruction {83  iType: InstructionType;84  opName: string;85  params: InstructionParameters;86  line: number;87  col: number;88  machineCode: number;89  constructor(opName: string, params: InstructionParameters, pos: [number, number]) {90    this.iType = operations[opName][0];91    this.opName = opName;92    this.params = params;93    this.line = pos[0];94    this.col = pos[1];95    this.machineCode = 0;96  }97  encode(index: number, symbols: SymbolTable) {98    // convert string offset to immediate99    // calculate machinecode100    if (typeof(this.params.offset) == "string") {101      this.params.imm = symbols[this.params.offset] - (index*4); 102    }103    if (this.params.symbol) {104      this.params.imm = symbols[this.params.symbol] - ((index-1)*4); // = symbol - PC105    }106    if (this.params.macro == "hi") {107      this.params.imm = ((this.params.imm >>> 12) + getBits(this.params.imm, 12, 11)) << 12;108      // la rd, symbol =>109      // auipc rd, delta[31:12] + delta[11] where delta = symbol - PC110      // addi rd, rd, delta[11:0]111    }112    const setCode = (code: number, field: string, value: number) => {113      const [lo, mask] = instructionFields[field];114      return (code & ~(mask << lo)) | ((value & mask) << lo);115    }116    const [fmt, opcode, funct3, funct7] = operations[this.opName];117    let code = 0;118    code = setCode(code, "opcode", opcode)119    switch (this.iType) {120      case "I":121        code = setCode(code, "funct3", funct3);122        code = setCode(code, "rd", this.params.rd);123        code = setCode(code, "rs1", this.params.rs1);124        code = setCode(code, "imm_11_0", this.params.imm);125        break;126      case "R":127        code = setCode(code, "funct3", funct3);128        code = setCode(code, "funct7", funct7);129        code = setCode(code, "rd", this.params.rd);130        code = setCode(code, "rs1", this.params.rs1);131        code = setCode(code, "rs2", this.params.rs2);132        break;133      case "S":134        code = setCode(code, "funct3", funct3);135        code = setCode(code, "rs1", this.params.rs1);136        code = setCode(code, "rs2", this.params.rs2);137        code = setCode(code, "imm_4_0", this.params.imm);138        code = setCode(code, "imm_11_5", this.params.imm >>> 5);139        break;140      case "B":141        code = setCode(code, "funct3", funct3);142        code = setCode(code, "rs1", this.params.rs1);143        code = setCode(code, "rs2", this.params.rs2);144        code = setCode(code, "imm_11b", this.params.imm >>> 11);145        code = setCode(code, "imm_4_1", this.params.imm >>> 1);146        code = setCode(code, "imm_10_5", this.params.imm >>> 5);147        code = setCode(code, "imm_12", this.params.imm >>> 12);  148        break;149      case "J":150        code = setCode(code, "rd", this.params.rd);151        code = setCode(code, "imm_19_12", this.params.imm >>> 12);152        code = setCode(code, "imm_11j", this.params.imm >>> 11);153        code = setCode(code, "imm_10_1", this.params.imm >>> 1);154        code = setCode(code, "imm_20", this.params.imm >>> 20);155        break;156      case "U":157        code = setCode(code, "rd", this.params.rd);158        code = setCode(code, "imm_31_12", this.params.imm >>> 12);159        break;160      default:161        throw new Error();162    }163    this.machineCode = code >>> 0;164  }165  formatMachineCode() {166    return "0x" + this.machineCode.toString(16).padStart(8,"0");167  }168  formatInstruction() {169    const xs = this.machineCode.toString(2).padStart(32, "0");170    switch (this.iType) {171      case "R":172      case "S":173      case "B":174        return  xs.slice(31-31, 31-25+1) + 175          "_" + xs.slice(31-24, 31-20+1) +176          "_" + xs.slice(31-19, 31-15+1) +177          "_" + xs.slice(31-14, 31-12+1) +178          "_" + xs.slice(31-11, 31-7+1) +179          "_" + xs.slice(31-6, 31-0+1);180      case "I":181        return  xs.slice(31-31, 31-20+1) + 182          "_" + xs.slice(31-19, 31-15+1) +183          "_" + xs.slice(31-14, 31-12+1) +184          "_" + xs.slice(31-11, 31-7+1) +185          "_" + xs.slice(31-6,  31-0+1);186      case "J":187      case "U":188        return  xs.slice(31-31, 31-12+1) + 189          "_" + xs.slice(31-11, 31-7+1) +190          "_" + xs.slice(31-6,  31-0+1);191      default:192        throw new Error();193    }194  }...

mapping.js

Source:mapping.js

1const OPCODE_TO_TYPE = {2  '0000011': 'I',3  '0010011': 'I',4  '0010111': 'U',5  '0100011': 'S',6  '0110011': 'R',7  '0110111': 'U',8  '1100011': 'B',9  '1100111': 'I',10  '1101111': 'J',11  '1110011': 'I',12  '0110011': 'R',13  '1010011': 'R',14  '0000111': 'I',15  '1010011': 'R',16  '0100111': 'S',17  '1110011': 'R'18}19/*20 * type: (instruction) => [rd, rs1, rs2, funct3, funct7, imm]21 */22const TYPE_PARSE = {23  'R': i => ([i.slice(20, 25), i.slice(12, 17), i.slice(7, 12), i.slice(17, 20), i.slice(0, 7), undefined]),24  'I': i => ([i.slice(20, 25), i.slice(12, 17), undefined     , i.slice(17, 20), undefined    , i[0].repeat(20) + i.slice(0, 12)]),25  'S': i => ([undefined      , i.slice(12, 17), i.slice(7, 12), i.slice(17, 20), undefined    , i[0].repeat(20) + i.slice(0, 7) + i.slice(20, 25)]),26  'J': i => ([i.slice(20, 25), undefined      , undefined     , undefined      , undefined    , i[0].repeat(12) + i.slice(12, 20) + i[11] + i.slice(1, 11) + '0']),27  'B': i => ([undefined      , i.slice(12, 17), i.slice(7, 12), i.slice(17, 20), undefined    , i[0].repeat(20) + i[24] + i.slice(1, 7) + i.slice(20, 24) + '0']),28  'U': i => ([i.slice(20, 25), undefined      , undefined     , undefined      , undefined    , i.slice(0, 20)])29}30/*31 * REGISTER[i] = [ 'name', 'use' ]32 */33const REGISTERS = [34  [ 'zero', 'The constant value 0'             ],35  [ 'ra'  , 'Return Address'                   ],36  [ 'sp'  , 'Stack Pointer'                    ],37  [ 'gp'  , 'Global Pointer'                   ],38  [ 'tp'  , 'Thread Pointer'                   ],39  [ 't0'  , 'Temporary Register'               ],40  [ 't1'  , 'Temporary Register'               ],41  [ 't2'  , 'Temporary Register'               ],42  [ 's0'  , 'Saved Register/Frame Pointer'     ],43  [ 's1'  , 'Saved Register'                   ],44  [ 'a0'  , 'Function Argument/Return Value'   ],45  [ 'a1'  , 'Function Argument/Return Value'   ],46  [ 'a2'  , 'Function Argument'                ],47  [ 'a3'  , 'Function Argument'                ],48  [ 'a4'  , 'Function Argument'                ],49  [ 'a5'  , 'Function Argument'                ],50  [ 'a6'  , 'Function Argument'                ],51  [ 'a7'  , 'Function Argument'                ],52  [ 's2'  , 'Saved Register'                   ],53  [ 's3'  , 'Saved Register'                   ],54  [ 's4'  , 'Saved Register'                   ],55  [ 's5'  , 'Saved Register'                   ],56  [ 's6'  , 'Saved Register'                   ],57  [ 's7'  , 'Saved Register'                   ],58  [ 's8'  , 'Saved Register'                   ],59  [ 's9'  , 'Saved Register'                   ],60  [ 's10' , 'Saved Register'                   ],61  [ 's11' , 'Saved Register'                   ],62  [ 't3'  , 'Temporary Register'               ],63  [ 't4'  , 'Temporary Register'               ],64  [ 't5'  , 'Temporary Register'               ],65  [ 't6'  , 'Temporary Register'               ]66]67/*68 * 'opcode + funct3 + funct7': [ 'mnemonic', 'name' ]69 */70const INSTRUCTIONS = {71  '00000110000000000': [ 'lb rd,imm(rs1)'   , 'Load Byte'                 ],72  '00000110010000000': [ 'lh rd,imm(rs1)'   , 'Load Halfword'             ],73  '00000110100000000': [ 'lw rd,imm(rs1)'   , 'Load Word'                 ],74  '00000111000000000': [ 'lbu rd,imm(rs1)'  , 'Load Byte Unsigned'        ],75  '00000111010000000': [ 'lhu rd,imm(rs1)'  , 'Load Halfword Unsigned'    ],76  '00100110000000000': [ 'addi rd,rs1,imm'  , 'Add Immediate'             ],77  '00100110010000000': [ 'slli rd,rs1,imm'  , 'Shift Left Logical Imm'    ],78  '00100110100000000': [ 'slti rd,rs1,imm'  , 'Set Less Than Immediate'   ],79  '00100110110000000': [ 'sltiu rd,rs1,imm' , 'Set Less Than Imm Unsig'   ],80  '00100111000000000': [ 'xori rd,rs1,imm'  , 'XOR Immediate'             ],81  '00100111010000000': [ 'srli rd,rs1,imm'  , 'Shift Right Logical Imm'   ],82  '00100111010100000': [ 'srai rd,rs1,imm'  , 'Shift Right Arith Imm'     ],83  '00100111100000000': [ 'ori rd,rs1,imm'   , 'OR Immediate'              ],84  '00100111110000000': [ 'andi rd,rs1,imm'  , 'AND Immediate'             ],85  '00101110000000000': [ 'auipc rd,imm'     , 'Add Upper Immediate to PC' ],86  '01000110000000000': [ 'sb rs2,imm(rs1)'  , 'Store Byte'                ],87  '01000110010000000': [ 'sh rs2,imm(rs1)'  , 'Store Halfword'            ],88  '01000110100000000': [ 'sw rs2,imm(rs1)'  , 'Store Word'                ],89  '01100110000000000': [ 'add rd,rs1,rs2'   , 'Add'                       ],90  '01100110000100000': [ 'sub rd,rs1,rs2'   , 'Subtract'                  ],91  '01100110010000000': [ 'sll rd,rs1,rs2'   , 'Shift Left Logical'        ],92  '01100110100000000': [ 'slt rd,rs1,rs2'   , 'Set Less Than'             ],93  '01100110110000000': [ 'sltu rd,rs1,rs2'  , 'Set Less Than Unsigned'    ],94  '01100111000000000': [ 'xor rd,rs1,rs2'   , 'XOR'                       ],95  '01100111010000000': [ 'srl rd,rs1,rs2'   , 'Shift Right Logical'       ],96  '01100111010100000': [ 'sra rd,rs1,rs2'   , 'Shift Right Arithmetic'    ],97  '01100111100000000': [ 'or rd,rs1,rs2'    , 'OR'                        ],98  '01100111110000000': [ 'and rd,rs1,rs2'   , 'AND'                       ],99  '01101110000000000': [ 'lui rd,imm'       , 'Load Upper Immediate'      ],100  '11000110000000000': [ 'beq rs1,rs2,imm'  , 'Branch if Equal'           ],101  '11000110010000000': [ 'bne rs1,rs2,imm'  , 'Branch if Not Equal'       ],102  '11000111000000000': [ 'blt rs1,rs2,imm'  , 'Branch if Less Than'       ],103  '11000111010000000': [ 'bge rs1,rs2,imm'  , 'Branch Greater or Equal'   ],104  '11000111100000000': [ 'bltu rs1,rs2,imm' , 'Branch Less Than Unsign'   ],105  '11000111110000000': [ 'bgeu rs1,rs2,imm' , 'Branch Great or Eq Unsign' ],106  '11001110000000000': [ 'jalr rd,rs1,imm'  , 'Jump & Link Register'      ],107  '11011110000000000': [ 'jal rd,imm'       , 'Jump & Link'               ],108  '11100110000000000': [ 'ecall'            , 'Environment CALL'          ],109  '11100110010000000': [ 'csrrw rd,CSR,rs1' , 'CSR Read & Write'          ],110  '11100110100000000': [ 'csrrs rd,CSR,rs1' , 'CSR Read & Set'            ],111  '11100110110000000': [ 'csrrc rd,CSR,rs1' , 'CSR Read & Clear'          ],112  '11100111010000000': [ 'csrrwi rd,CSR,imm', 'CSR Read & Write Imm'      ],113  '11100111100000000': [ 'csrrsi rd,CSR,imm', 'CSR Read & Set Imm'        ],114  '11100111110000000': [ 'csrrci rd,CSR,imm', 'CSR Read & Clear Imm'      ],115  '01100110000000001': [ 'mul rd,rs1,rs2'   , 'Multiply'                  ],116  '01100110010000001': [ 'mulh rd,rs1,rs2'  , 'Multiply upper Half'       ],117  '01100110100000001': [ 'mulhsu rd,rs1,rs2', 'Mult upper Half Sign/Uns'  ],118  '01100110110000001': [ 'mulhu rd,rs1,rs2' , 'Mult upper Half Unsig'     ],119  '01100111000000001': [ 'div rd,rs1,rs2'   , 'Divide'                    ],120  '01100111010000001': [ 'divu rd,rs1,rs2'  , 'Divide Unsigned'           ],121  '01100111100000001': [ 'rem rd,rs1,rs2'   , 'Remainder'                 ],122  '01100111110000001': [ 'remu rd,rs1,rs2'  , 'Remainder Unsigned'        ]...

Using AI Code Generation

1var wpt = require('./wpt');2wpt.rs1();3wpt.rs2();4wpt.rs3();5exports.rs1 = function() {6}7exports.rs2 = function() {8}9exports.rs3 = function() {10}11var wpt = require('./wpt');12wpt.rs1();13wpt.rs2();14wpt.rs3();

Using AI Code Generation

1console.log(wpt.rs1("Hello World!"));2console.log(wpt.rs2("Hello World!"));3console.log(wpt.rs3("Hello World!"));4console.log(wpt.rs4("Hello World!"));5console.log(wpt.rs5("Hello World!"));6console.log(wpt.rs6("Hello World!"));7console.log(wpt.rs7("Hello World!"));8console.log(wpt.rs8("Hello World!"));9console.log(wpt.rs9("Hello World!"));10console.log(wpt.rs10("Hello World!"));11console.log(wpt.rs11("Hello World!"));12console.log(wpt.rs12("Hello World!"));13console.log(wpt.rs13("Hello World!"));14console.log(wpt.rs14("Hello World!"));15console.log(wpt.rs15("Hello World!"));16console.log(wpt.rs16("Hello World!"));17console.log(wpt.rs17("Hello World!"));18console.log(wpt.rs18("Hello World!"));19console.log(wpt.rs19("Hello World!"));20console.log(wpt.rs20("Hello World!"));21console.log(wpt.rs21("Hello World!"));22console.log(wpt.rs22("Hello World!"));

Using AI Code Generation

1var wpt = require('wpt');2var wpt = new WebPageTest('www.webpagetest.org');3    if (err) return console.log(err);4    console.log(data);5    wpt.getTestResults(data.data.testId, function(err, data) {6        if (err) return console.log(err);7        console.log(data);8    });9});

Using AI Code Generation

1var wpt = require('webpagetest');2var api = new wpt('www.webpagetest.org');3  if (err) {4    console.log(err);5  } else {6    console.log(data);7  }8});9var wpt = require('webpagetest');10var api = new wpt('www.webpagetest.org');11  if (err) {12    console.log(err);13  } else {14    console.log(data);15  }16});17var wpt = require('webpagetest');18var api = new wpt('www.webpagetest.org');19  if (err) {20    console.log(err);21  } else {22    console.log(data);23  }24});25var wpt = require('webpagetest');26var api = new wpt('www.webpagetest.org');27  if (err) {28    console.log(err);29  } else {30    console.log(data);31  }32});33var wpt = require('webpagetest');34var api = new wpt('www.webpagetest.org');35  if (err) {36    console.log(err);37  } else {38    console.log(data);39  }40});41var wpt = require('webpagetest');42var api = new wpt('www.webpagetest.org');

Using AI Code Generation

1var wpt = require('wpt');2var rs1 = new wpt('your api key');3    console.log(data);4    console.log('testId: ' + data.data.testId);5    console.log('ownerKey: ' + data.data.ownerKey);6    console.log('jsonUrl: ' + data.data.jsonUrl);7    console.log('userUrl: ' + data.data.userUrl);8    console.log('xmlUrl: ' + data.data.xmlUrl);9});10var wpt = require('wpt');11var rs2 = new wpt('your api key');12    console.log(data);13    console.log('testId: ' + data.data.testId);14    console.log('ownerKey: ' + data.data.ownerKey);15    console.log('jsonUrl: ' + data.data.jsonUrl);16    console.log('userUrl: ' + data.data.userUrl);17    console.log('xmlUrl: ' + data.data.xmlUrl);18});19var wpt = require('wpt');20var rs3 = new wpt('your api key');21    console.log(data);22    console.log('testId: ' + data.data.testId);23    console.log('ownerKey: ' + data.data.ownerKey);24    console.log('jsonUrl: ' + data.data.jsonUrl);25    console.log('userUrl: ' + data.data.userUrl);26    console.log('xmlUrl: ' + data.data.xmlUrl);27});28var wpt = require('wpt');29var rs4 = new wpt('your api key');30    console.log(data);31    console.log('testId: ' + data.data.testId);32    console.log('ownerKey: ' + data.data.ownerKey);33    console.log('jsonUrl: ' + data.data.jsonUrl);34    console.log('user

Using AI Code Generation

1var wpt = require('wpt');2var rs1 = wpt.runTest('www.google.com', function (err, data) {3  if (err) return console.error(err);4  console.log(data);5});6var wpt = require('wpt');7var rs2 = wpt.runTest('www.google.com', function (err, data) {8  if (err) return console.error(err);9  console.log(data);10});

Using AI Code Generation

1var wpt = require('webpagetest');2var test = new wpt('www.webpagetest.org', 'A.0d2e9f0b9e6c1d0d4f6b2f2b0d2b4e4e');3  if (err) return console.error(err);4  var testId = data.data.testId;5  console.log('Test id: ' + testId);6  test.getTestStatus(testId, function(err, data) {7    if (err) return console.error(err);8    console.log('Test completed? ' + data.data.completeTime);9  });10});11var wpt = require('webpagetest');12var test = new wpt('www.webpagetest.org', 'A.0d2e9f0b9e6c1d0d4f6b2f2b0d2b4e4e');13  if (err) return console.error(err);14  var testId = data.data.testId;15  console.log('Test id: ' + testId);16  test.getTestStatus(testId, function(err, data) {17    if (err) return console.error(err);18    console.log('Test completed? ' + data.data.completeTime);19  });20});

Automation Testing Tutorials

Learn to execute automation testing from scratch with LambdaTest Learning Hub. Right from setting up the prerequisites to run your first automation test, to following best practices and diving deeper into advanced test scenarios. LambdaTest Learning Hubs compile a list of step-by-step guides to help you be proficient with different test automation frameworks i.e. Selenium, Cypress, TestNG etc.